An SOI wafer is produced as follows, for example. An insulator film such as an oxide film (Box layer, which is to become a buried oxide film (insulator film)) is formed on at least one of a first silicon wafer (hereafter, called “bond wafer”, from which an SOI layer is formed) having at least one flattened and mirror-polished main surface and a second silicon wafer (hereafter, called “base wafer”, which is to become a support substrate). Each main surface of the two silicon wafers is bonded and joined to each other via the insulator film. After the wafers are subjected to a heat treatment to firmly join them, the other main surface opposite to the bonded main surface of the bond wafer is ground and polished to have a predetermined thickness, and thereby an SOI layer (an element fabrication layer) is formed on the insulator film, so that an SOI wafer is produced.
It is often the case that such a production method is mainly used for producing an SOI wafer having an SOI layer having a thickness of about 0.5 μm or more.
On the other hand, making an insulator film and an SOI layer thinner has been developed, and an SOI wafer having an SOI layer and an insulator film, which have a thickness of about 0.4 μm or less respectively, has also been produced. In this case, although the SOI wafer is difficult to be produced by the above method, a production method of an SOI wafer based on an ion implantation delamination method (also called “Smart Cut Method” (registered trademark)), for example, disclosed in Japanese Patent Laid-open (Kokai) Publication No. 5-211128, can be utilized.
In the ion implantation delamination method, for example, an insulator film is formed on at least one of a bond wafer made of silicon single crystal to form an SOI layer and a base wafer made of silicon single crystal to be an support substrate, a micro bubble layer is formed in the bond wafer by implanting gas ions from a main surface of the bond wafer. Then, the ion-implanted main surface of the bond wafer is bonded to a main surface of the base wafer via the insulator film, thereafter the bonded wafer is subjected to a heat treatment to delaminate the wafers at the micro bubble layer as a border, and the delaminating plane to form an SOI layer is subjected to a slight polishing to produce an SOI wafer.
For bond wafers used in the above two production method, there are commonly used wafers obtained from a silicon single crystal grown by a Czochralski method (hereafter, called “CZ method”), by which substrates having a large diameter can be produced at low cost (hereafter, such a wafer may be called “CZ wafer”).
However, defects called COP (Crystal Originated Particle) exist on a surface and the inside of the CZ wafer, and may become a problem in a device process.
The COP is one of crystal defects introduced in crystal growth, typically, is a void type defect having a regular octahedral structure (single type) shown in FIG. 2, and is generally formed with a size of 60–130 nm.
When a surface of a silicon wafer is measured by means of a particle counter directly after mirror-polishing or after cleaning the mirror-polished surface with a mixed solution of ammonia and a hydrogen peroxide solution, this COP 10 is detected as a bright spot together with real particles.
In addition, there also exists COP 11 having a double-connected structure (twin type) as shown in FIG. 3 or COP having a triple-connected structure (triplet type). It was revealed that these COPs are formed in the order of a size of 100–300 nm due to the fact that single type COPs grow in a cooling process of a growing single crystal.
If a CZ wafer having COPs is used as a bond wafer to produce an SOI wafer, the bond wafer has harmful effects on, for example, Time Dependent Dielectric Breakdown (TDDB) and Time Zero Dielectric Breakdown (TZDB) of an oxide film, which are important electric characteristics for devices.
Moreover, there are some cases that COPs existing on a surface to be bonded of a bond wafer penetrate an SOI layer and form pinholes. In such a case, for example, an insulator film separating a base wafer and an SOI layer is etched with an etchant in an etching process or an atmosphere gas in a heat treatment process intruding from the pinholes and steps are generated in a wiring process to cause breaking of a wire. Consequently, there was caused a problem such that yield of a device process was decreased.
In order to solve such a problem, there is disclosed in Japanese Patent Laid-open (Kokai) Publication No. 11-145436 a technique that a hydrogen annealed wafer, an intrinsic gettering wafer, or an epitaxial wafer, in which COPs near its surface are reduced or eliminated, is used as a bond wafer. When such a bond wafer in which COPs are reduced or eliminated is used to produce an SOI wafer, the SOI wafer containing no COP in the SOI layer can be obtained.
In this case, since the bond wafer with high quality and high cost as described above is needed, the base wafer with reduced cost is sometimes used. The base wafer used for the SOI wafer is required originally for supporting an SOI layer via an insulator film, thus, no element is formed on surface of the base wafer. Therefore, a wafer having COPs on its surface is used as the base wafer, and moreover, as disclosed in Japanese Patent Laid-open (Kokai) Publication No. 11-40786, a dummy-grade silicon wafer of which resistivity and the like do not meet product standards is also used as a base wafer. Since the dummy-grade silicon wafers are being marketed at about half the price of regular wafers, it has a great effect on reduction in cost.
However, even where the silicon wafer in which COPs are reduced as aforementioned is used as a bond wafer, when a thinner SOI layer and a thinner insulator film are formed to produce an SOI wafer which has been required recently, there are some cases that a considerable number of COPs are detected in the inspection of the SOI layer after completing the SOI wafer, and also there arose the phenomenon that a high quality wafer as expected can not be obtained.